6.3.2.2.1.1. fb0

display-fb {
    compatible = "zx,aic-framebuffer";
    #address-cells = <1>;
    #size-cells = <0>;
    fb0: fb@0 {
        reg = <0x0 0x0>;
    };
};

6.3.2.2.1.2. display engine

de0: de@18a00000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "zx,aic-de-v1.0";
    reg = <0x0 0x18a00000 0x0 0x1000>;
    interrupts-extended = <&plic0 59 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&cmu CLK_DE>, <&cmu CLK_PIX>;
    clock-names = "de0", "pix";
    resets = <&rst RESET_DE>;
    reset-names = "de0";
    mclk-rate = <200000000>;
};

6.3.2.2.1.3. rgb display interface

rgb0: rgb@18800000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "zx,aic-rgb-v1.0";
    reg = <0x0 0x18800000 0x0 0x1000>;
    clocks = <&cmu CLK_RGB>, <&cmu CLK_SCLK>;
    clock-names = "rgb0", "sclk";
    resets = <&rst RESET_RGB>;
    reset-names = "rgb0";
};

6.3.2.2.1.4. lvds display interface

lvds0: lvds@18810000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "zx,aic-lvds-v1.0";
    reg = <0x0 0x18810000 0x0 0x1000>;
    clocks = <&cmu CLK_LVDS>, <&cmu CLK_SCLK>;
    clock-names = "lvds0", "sclk";
    resets = <&rst RESET_LVDS>;
    reset-names = "lvds0";
};

6.3.2.2.1.5. mipi-dsi display interface

dsi0: dsi@18820000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "zx,aic-mipi-dsi-v1.0";
    reg = <0x0 0x18820000 0x0 0x1000>;
    clocks = <&cmu CLK_MIPIDSI>, <&cmu CLK_SCLK>;
    clock-names = "dsi0", "sclk";
    resets = <&rst RESET_MIPIDSI>;
    reset-names = "dsi0";
    interrupts-extended = <&plic0 56 IRQ_TYPE_LEVEL_HIGH>;
    data-lanes = <0 1 2 3>;
    lane-polarities = <0 0 0 0>;
};