11.2.3. 寄存器描述

11.2.3.1. 0x000 CAPLENGTH(EHCI)

默认值：0x01000010			CAPLENGTH寄存器（CAPLENGTH）
位域	类型	默认值	描述
31:16	R	0x0100	EHCI接口版本号，高八位代表EHCI的主版本号，低八位位EHCI的次版本 号。
15:8	-	-	-
7:0	R	0x10	指示USB Host工作寄存器的偏移地址。

11.2.3.2. 0x004 HCSPARAMS(EHCI)

默认值：0x00001111			HCSPARAMS寄存器（HCSPARAMS）
位域	类型	默认值	描述
31:24	-	-	-
23:20	R	0x0	Debug Port Number (Optional) 此域用于表示Debug Port Number。
19:17	-	-	-
16	R	0x0	P_INDICATOR Port Indicators This bit indicates whether the ports support port indicator control. When this bit is a one, the port status and control registers include a read/writeable field for controlling the state of the port indicator.
15:12	R	0x1	N_CC Number of Companion Controller，表示此USB 2.0 Host Controller 包括了多少个Companion Controller，这里只有一个OHCI Host Controlller。
11:8	R	0x1	N_PCC Number of ports supported per companion host controller， 表示每个Companion Controller支持的端口数，这里只有一个端口。
7	R	0x0	Port Routing Rules 表示端口与Companion Controller的映射方式 0x0：The first N_PCC ports are routed to the lowest numbered function companion host controller, the next N_PCC port are routed to the next lowest function companion controller , and so on. 第一个Port对应低号的companion Controller。 0x1：The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP-PORTROUTE array.
6:5	-	-	-
4	R	0x1	PPC Port Power Control，此位指示此Host Controller是否实现端口 电源控制开关。
3:0	R	0x1	N_PORTS Number of physical downstream ports，此域表示此Host Controller具有多少个下行的物理端口。

11.2.3.3. 0x008 HCCPARAMS(EHCI)

默认值：0x00001400			USB PHY接口寄存器（USB PHY Interface）
位域	类型	默认值	描述
31:16	-	-	-
15:8	R	0xA0	EECP EHCI Extended Capabilities Pointer，此域用于指示capabilities 清单。
7:4	R	0x1	Isochronous Scheduling Threshold，同步调度阈值 When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame.
3	-	-	-
2	R	0x0	Asynchronous Schedule Park Capability，此位表示是否支持 Asynchronous Schedule Park功能 0x0：the host controller doesn’t support the park feature for high-speed queue heads in the Asynchronous Schedule. 0x1：the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.
1	R	0x0	Programmable Frame List Flag，此位表示是否支持可Frame List Size是否可编程 0x0：System software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and should be set to zero. 0x1：System software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous.
0	R	0x0	64-bit Addressing Capability，此位表示32bit地址还是64bit地址。 0x0：data structures using 32-bit address memory pointers 0x1：data structures using 64-bit address memory pointers

11.2.3.4. 0x010 USBCMD(EHCI)

默认值：0x00080000			USBCMD寄存器（USBCMD）
位域	类型	默认值	描述
31:24	-	-	-
23:16	R/W	0x08	Interrupt Threshold Control，中断阈值控制 This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. 0x00：Reserved 0x01：1 micro-frame 0x02：2 micro-frames 0x04：4 micro-frames 0x08：8 micro-frames 0x10：16 micro-frames 0x20：32 micro-frames 0x40：64 micro-frames Any other value in this register yields undefined results.
15:12	-	-	-
11	RO	0x0	Asynchronous Schedule Park Mode Enable 不支持此功能 If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.
10	-	-	-
9:8	RO	0x0	Asynchronous Schedule Park Mode Count (OPTIONAL) 不支持此功能 If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior.
7	R/W	0x0	Light Host Controller Reset (OPTIONAL) EHCI控制器轻复位 This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as a one indicates the Light Host Controller Reset has not yet completed. If not implemented a read of this field will always return a zero.
6	R/W	0x0	Interrupt on Async Advance Doorbell 使能产生异步调度器向前中断（对应USBSTS的中断状态位Interrupt on Async Advance ） 0：不产生中断 1：产生中断 This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one. Software should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results.
5	R/W	0x0	Asynchronous Schedule Enable，异步调度使能 This bit controls whether the host controller skips processing the Asynchronous Schedule. 0x0：Do not process the Asynchronous Schedule 0x1：Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
4	R/W	0x0	Periodic Schedule Enable，周期调度使能 This bit controls whether the host controller skips processing the Periodic Schedule. 0x0：Do not process the Periodic Schedule 0x1：Use the PERIODICLISTBASE register to access the Periodic Schedule.
3:2	RO	0x0	Frame List Size 此功能不支持 This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index. Values mean: 0b00：1024 elements (4096 bytes) Default value 0b01：512 elements (2048 bytes) 0b10：256 elements (1024 bytes) – for resource-constrained environments 0b11：Reserved
1	R/WAC	0x0	Host Controller Reset (HCRESET) EHCI控制复位，复位完成后会自动清0 This control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. PCI Configuration registers are not affected by this reset. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects. Software must reinitialize the host controller in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
0	R/W	0x0	Run/Stop (RS) 0x1：Run，EHCI调度器工作 0x0：Stop，EHCI调度器停止 When set to a 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears the Run bit. The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). Doing so will yield undefined results.

11.2.3.5. 0x014 USBSTS(EHCI)

默认值：0x00001000			USBSTS寄存器（USBSTS）
位域	类型	默认值	描述
31:16	/		/
15	RO	0x0	Asynchronous Schedule Status 此位指示当前异步调度的状态 0x0：异步调度未使能 0x1：异步调度使能 The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
14	RO	0x0	Periodic Schedule Status 此位指示当前周期调度的状态 0x0：同步调度未使能 0x1：同步调度使能 The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
13	RO	0x0	Reclamation 此位用于检测异步调度是否为空。
12	RO	0x1	HCHalted 此位用于指示EHCI的调度器是否停止。 0x0：EHCI的调度器工作 0x1：EHCI的调度器停止
11:6	/	/	/
5	R/W1C	0x0	Interrupt on Async Advance 异步调度器向前中断 System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.
4	R/W1C	0x0	Host System Error EHCI系统错误中断 0x0：无中断 0x1：出现中断，此时EHCI会将Run/Stop Bit清0，停止调度器的工作
3	R/W1C	0x0	Frame List Rollover 帧链表溢出中断 0x0：无中断 0x1：出现中断，帧链表溢出 The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
2	R/W1C	0x0	Port Change Detect 端口归属变化中断 0x0：无中断 0x1：出现中断，端口归属出现变化 The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero (see Section 2.3.9) has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port’s Port Owner bit. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
1	R/W1C	0x0	USB Error Interrupt (USBERRINT) USB错误中断 0x0：无中断 0x1：出现中断 The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
0	R/W1C	0x0	USB Interrupt (USBINT) 0x0：无中断 0x1：出现中断 The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).

11.2.3.6. 0x018 USBINTR(EHCI)

默认值：0x00000000			FRINDEX寄存器（FRINDEX）
位域	类型	默认值	描述
31:6	-	-	-
5	R/W	0x0	Interrupt on Async Advance Enable 异步调度器向前中断使能 When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit
4	R/W	0x0	Host System Error Enable EHCI系统错误中断使能 When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit.
3	R/W	0x0	Frame List Rollover Enable 帧链表溢出中断使能 When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
2	R/W	0x0	Port Change Interrupt Enable. 端口归属变化中断使能 When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit.
1	R/W	0x0	USB Error Interrupt Enable USB错误中断使能 When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit.
0	R/W	0x0	USB Interrupt Enable USB中断使能 When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit.

11.2.3.7. 0x01C FRINDEX(EHCI)

默认值：0x00000000			FRINDEX寄存器（FRINDEX）
位域	类型	默认值	描述
31:14	-	-	-
13:0	R/W	0x0	Frame Index 帧索引号 The value in this register increments at the end of each time frame (e.g.micro-frame). Bits [12:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List

11.2.3.8. 0x024 PERIODICLISTBASE(EHCI)

默认值：0x00000000			PERIODICLISTBASE寄存器（PERIODICLISTBASE）
位域	类型	默认值	描述
31:12	R/W	0x0	Base Address 此域对应空间地址的Bit[31:12] This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. These bits correspond to memory address signals [31:12], respectively.
11:0	R/W	0x0	Reserved Must be written as 0s.

11.2.3.9. 0x028 ASYNCLISTADDR(EHCI)

默认值：0x00000000			ASYNCLISTADDR寄存器（ASYNCLISTADDR）
位域	类型	默认值	描述
31:5	R/W	0x0	Link Pointer Low (LPL). 此域为下一个将要被执行的异步QH的地址。 This 32-bit register contains the address of the next asynchronous queue head to be executed. These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
4:0	-	-	-

11.2.3.10. 0x050 CONFIGFLAG(EHCI)

默认值：0x00000000			CONFIGFLAG寄存器（CONFIGFLAG）
位域	类型	默认值	描述
31:1	-	-	-
0	R/W	0x0	Configure Flag (CF) 配置标志位 Host software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. 0x0：Port0选择OHCI 0x1：Port0选择EHCI

11.2.3.11. 0x054 PORTSC(EHCI)

默认值：0x00002000			PORTSC寄存器（PORTSC）
位域	类型	默认值	描述
31:23	-	-	-
22	R/W	0x0	Wake on Over-current Enable 使能过流唤醒 0x0：不使能 0x1：使能，出现过流的情况将唤醒HOST Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power is zero.
21	R/W	0x0	Wake on Disconnect Enable (WKDSCNNT_E) 使能断开唤醒 0x0：不使能 0x1：使能，出现端口断开的情况将唤醒HOST Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power is zero.
20	R/W	0x0	Wake on Connect Enable (WKCNNT_E) 使能连接唤醒 0x0：不使能 0x1：使能，出现端口连接的情况将唤醒HOST Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power is zero.
19:16	R/W	0x0	Port Test Control 端口测试控制 0x0：Test mode未使能 0x1：Test J_STATE 0x2：Test K_STATE 0x3：Test SE0_NAK 0x4：Test Packet 0x5：Test FORCE_ENABLE
15:14	-	-	-
13	R/W	0x1	Port Owner 端口归属 This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port.
12	R/W	0x0	Port Power (PP) 端口电源控制 0x0：电源开关断开 0x1：电源开关闭合 When power is not available on a port (i.e. PP equals a 0), the port is non- functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
11:10	RO	0x0	Line Status These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. 0x0：SE0 Not Low-speed device, perform EHCI reset 0x1：K-state Low-speed device, release ownership of port 0x2：J-state Not Low-speed device, perform EHCI reset 0x3：Undefined Not Low-speed device, perform EHCI reset. This value of this field is undefined if Port Power is zero.
9	-	-	-
8	R/W	0x0	Port Reset 端口复位 0x0：端口不处于复位状态 0x1：使能端口进行复位 When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. This field is zero if Port Power is zero.
7	R/W	0x0	Suspend 0x0：端口不处于Suspend状态 0x1：使能端口进入Suspend状态 Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0x0X:Disable 0x10:Enable 0x11:Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. A write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when: • Software sets the Force Port Resume bit to a zero (from a one). • Software sets the Port Reset bit to a one (from a zero). If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This field is zero if Port Power is zero.
6	R/W	0x0	Force Port Resume 强制端口Resume 0x0：无操作 0x1：强制端口Resume This functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit. Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this bit remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return to high- speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to the high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. This field is zero if Port Power is zero.
5	R/W1C	0x0	Over-current Change 端口过流状态变化 0x0：端口过流状态为变化 0x1：端口出现过流状态变化 Software clears this bit by writing a one to this bit position.
4	RO	0x0	Over-current Active 端口过流 0x1：This port currently has an over-current condition. 0x0：This port does not have an over-current condition. This bit will automatically transition from a one to a zero when the over current condition is removed.
3	R/W1C	0x0	Port Enable/Disable Change 端口使能/禁止变化 0x1：Port enabled/disabled status has changed. 0x0：No change. For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point. Software clears this bit by writing a 1 to it. This field is zero if Port Power is zero.
2	R/W	0x0	Port Enabled/Disabled 端口使能/禁止 0x1：Enable，只有在端口实现RESET后，设备枚举完成为HS设备时，此位置1， 软件不能对此位写1。 0x0：Disable，端口RESET后，设备枚举完成为非HS设备。 Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. This field is zero if Port Power is zero.
1	R/WC	0x0	Connect Status Change 端口连接状态发生变化 0x1：Change in Current Connect Status. 0x0：No change. Indicates a change has occurred in the port’s Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be “setting” an already-set bit (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. This field is zero if Port Power is zero.
0	RO	0x0	Current Connect Status 当前端口连接状态 0x1：Device is present on port 0x0：No device is present. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power is zero.

11.2.3.12. 0x400 HcRevision(OHCI)

默认值：0x00000110			HcRevision寄存器（HcRevision）
位域	类型	默认值	描述
31:9	-	-	-
8	R	0x1	LEGACY_SUPPORT
7:0	R	0x10	Revision OHCI版本 This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this HC. For example, a value of 11h corresponds to version 1.1. All of the HC implementations that are compliant with this specification will have a value of 10h.

11.2.3.13. 0x404 HcControl(OHCI)

默认值：0x00000000			HcControl寄存器（HcControl）
位域	类型	默认值	描述
31:11	-	-	-
10	R/W	0x0	RWE RemoteWakeupEnable 远程唤醒使能 This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt.
9	R/W	0x0	RWC RemoteWakeupConnected This bit indicates whether HC supports remote wakeup signaling. If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST. HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wakeup signaling of the host system is host-bus-specific and is not described in this specification.
8	R/W	0x0	IR InterruptRouting，中断通路 0x0：all interrupts are routed to the normal host bus interrupt mechanism 0x1：all interrupts are routed to the System Management Interrupt This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set, interrupts are routed to the System Management Interrupt. HCD clears this bit upon a hardware reset, but it does not alter this bit upon a software reset. HCD uses this bit as a tag to indicate the ownership of HC.
7:6	R/W	0x0	HCFS HostControllerFunctionalState for USB USB Host控制器的功能状态 0x0: USB RESET 0x1: USB RESUME 0x2: USB OPERATIONAL 0x3: USB SUSPEND A transition to USB OPERATIONAL from another state causes SOF generation to begin 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the StartofFrame field of HcInterruptStatus. This field may be changed by HC only when in the USBSUSPEND state. HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports.
5	R/W	0x0	BLE BulkListEnable，Bulk链表使能 This bit is set to enable the processing of the Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur after the next SOF. HC checks this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list.
4	R/W	0x0	CLE ControlListEnable，控制链表使能 This bit is set to enable the processing of the Control list in the next Frame. If cleared by HCD, processing of the Control list does not occur after the next SOF. HC must check this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list.
3	R/W	0x0	IE IsochronousEnable，同步端点描述符使能 This bit is used by HCD to enable/disable processing of isochronous EDs. While processing the periodic list in a Frame, HC checks the status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC continues processing the EDs. If cleared (disabled), HC halts processing of the periodic list (which now contains only isochronous EDs) and begins processing the Bulk/Control lists. Setting this bit is guaranteed to take effect in the next Frame (not the current Frame).
2	R/W	0x0	PLE PeriodicListEnable，周期链表使能 This bit is set to enable the processing of the periodic list in the next Frame. If cleared by HCD, processing of the periodic list does not occur after the next SOF. HC must check this bit before it starts processing the list.
1:0	R/W	0x0	CBSR ControlBulkServiceRatio，Control Bulk服务比 This specifies the service ratio between Control and Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this value. （Control EP描述符与Bulk EP描述符之比） 0x0：(1:1) 0x1：(2:1) 0x2：(3:1) 0x3：(4:1)

11.2.3.14. 0x408 HcCommandStatus(OHCI)

默认值：0x00000000			HcCommandStatus寄存器（HcCommandStatus）
位域	类型	默认值	描述
31:18	-	-	-
17:16	R/W	0x0	SOC SchedulingOverrunCount，调度器溢出计数 These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems.
15:3	-	-	-
3	R/W	0x0	OCR OwnershipChangeRequest，归属变化请求信号 This bit is set by an OS HCD to request a change of control of the HC. When set HC will set the OwnershipChange field in HcInterruptStatus. After the changeover, this bit is cleared and remains so until the next request from OS HCD.
2	R/W	0x0	BLF BulkListFilled，Bulk链表填入TD This bit is used to indicate whether there are any TDs on the Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. When HC begins to process the head of the Bulk list, it checks BF. As long as BulkListFilled is 0, HC will not start processing the Bulk list. If BulkListFilled is 1, HC will start processing the Bulk list and will set BF to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 causing the Bulk list processing to continue. If no TD is found on the Bulk list, and if HCD does not set BulkListFilled, then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop.
1	R/W	0x0	CLF ControlListFilled，控制链表填入TD This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control list. When HC begins to process the head of the Control list, it checks CLF. As long as ControlListFilled is 0, HC will not start rocessing the Control list. If CF is 1, HC will start processing he Control list and will set ControlListFilled to 0. If HC finds a D on the list, then HC will set ControlListFilled to 1 causing the Control list processing to continue. If no TD is found on the Control list, and if the HCD does not set ControlListFilled, then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will stop.
0	R/W	0x0	HCR HostControllerReset，OHCI软复位 This bit is set by HCD to initiate a software reset of HC. Regardless of the functional state of HC, it moves to the USBSUSPEND state in which most of the operational registers are reset except those stated otherwise; e.g., the InterruptRouting field of HcControl, and no Host bus accesses are allowed. This it is cleared by HC upon the completion of the reset operation. The reset operation must be completed within 10 ms. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports.

11.2.3.15. 0x40C HcInterruptStatus

默认值：0x00000000			HcInterruptStatus寄存器（HcInterruptStatus）
位域	类型	默认值	描述
31	-	-	-
30	R/W	0x0	OC OwnershipChange，归属状态变化 This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. This event, when unmasked, will always generate an System Management Interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is not implemented.
29:7	-	-	-
6	R/W	0x0	RHSC RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed.
5	R/W	0x0	FNO FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
4	R/W	0x0	UE UnrecoverableError This bit is set when HC detects a system error not related to USB. HC should not proceed with any processing nor signaling before the system error has been corrected. HCD clears this bit after HC has been reset.
3	R/W	0x0	RD ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. It is the transition from no resume signaling to resume signaling causing this bit to be set. This bit is not set when HCD sets the USBRESUME state.
2	R/W	0x0	SF StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. HC also generates a SOF token at the same time.
1	R/W	0x0	WDH WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. HCD should only clear this bit after it has saved the content of HccaDoneHead.
0	R/W	0x0	SO SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented.

11.2.3.16. 0x410 HcInterruptEnable

默认值：0x00000000			HcInterruptEnable寄存器（HcInterruptEnable）
位域	类型	默认值	描述
31	R/W	0x0	MIE A ‘0’ written to this field is ignored by HC. A ‘1’ written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable.
30	R/W	0x0	OC 0x0：Ignore 0x1：Enable interrupt generation due to Ownership Change.
29:7	-	-	-
6	R/W	0x0	RHSC 0x0：Ignore 0x1：Enable interrupt generation due to Root Hub Status Change.
5	R/W	0x0	FNO 0x0：Ignore 0x1：Enable interrupt generation due to Frame Number Overflow.
4	R/W	0x0	UE 0x0：Ignore 0x1：Enable interrupt generation due to Unrecoverable Error.
3	R/W	0x0	RD 0x0：Ignore 0x1：Enable interrupt generation due to Resume Detect.
2	R/W	0x0	SF 0x0：Ignore 0x1：Enable interrupt generation due to Start of Frame.
1	R/W	0x0	WDH 0x0：Ignore 0x1：Enable interrupt generation due to HcDoneHead Writeback.
0	R/W	0x0	SO 0x0：Ignore 0x1：Enable interrupt generation due to Scheduling Overrun.

11.2.3.17. 0x414 HcInterruptDisable

默认值：0x00000000			HcInterruptDisable寄存器（HcInterruptDisable）
位域	类型	默认值	描述
31	R/W	0x0	MIE A ‘0’ written to this field is ignored by HC. A ‘1’ written to this field disables interrupt generation due to events specified in the other bits of this register. This field is set after a hardware or software reset.
30	R/W	0x0	OC 0x0：Ignore 0x1：Disable interrupt generation due to Ownership Change.
29:7	-	-	-
6	R/W	0x0	RHSC 0x0：Ignore 0x1：Disable interrupt generation due to Root Hub Status Change.
5	R/W	0x0	FNO 0x0：Ignore 0x1：Disable interrupt generation due to Frame Number Overflow.
4	R/W	0x0	UE 0x0：Ignore 0x1：Disable interrupt generation due to Unrecoverable Error.
3	R/W	0x0	RD 0x0：Ignore 0x1：Disable interrupt generation due to Resume Detect.
2	R/W	0x0	SF 0x0：Ignore 0x1：Disable interrupt generation due to Start of Frame.
1	R/W	0x0	WDH 0x0：Ignore 0x1：Disable interrupt generation due to HcDoneHead Writeback.
0	R/W	0x0	SO 0x0：Ignore 0x1：Disable interrupt generation due to Scheduling Overrun.

11.2.3.18. 0x418 HcHCCA

默认值：0x00000000			HcHCCA寄存器（HcHCCA）
位域	类型	默认值	描述
31:8	R/W	0x0	HCCA[31:8] This is the base address of the Host Controller Communication Area.
7:0	R	0x0	HCCA[7:0] The alignment is evaluated by examining the number of zeroes in the lower order bits. The minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return ‘0’ when read.

11.2.3.19. 0x41C HcPeriodCurrentED

默认值：0x00000000			HcPeriodCurrentED寄存器（HcPeriodCurrentED）
位域	类型	默认值	描述
31:4	R/W	0x0	PCED[31:4] PeriodCurrentED This is used by HC to point to the head of one of the Periodic lists which will be processed in the current Frame. The content of this register is updated by HC after a periodic ED has been processed. HCD may read the content in determining which ED is currently being processed at the time of reading.
3:0	R	0x0	PCED[3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the PCED, through bit 0 to bit 3 must be zero in this field.

11.2.3.20. 0x420 HcControlHeadED

默认值：0x00000000			HcControlHeadED寄存器（HcControlHeadED）
位域	类型	默认值	描述
31:4	R/W	0x0	CHED[31:4] ControlHeadED HC traverses the Control list starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of HC.
3:0	R	0x0	CHED[3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the CHED, through bit 0 to bit 3 must be zero in this field.

11.2.3.21. 0x0424 HcControlCurrentED

默认值：0x00000000			HcControlCurrentED寄存器（HcControlCurrentED）
位域	类型	默认值	描述
31:4	R/W	0x0	CCED[31:4] ControlCurrentED This pointer is advanced to the next ED after serving the present one. HC will continue processing the list from where it left off in the last Frame. When it reaches the end of the Control list, HC checks the ControlListFilled of in HcCommandStatus. If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared. When set, HCD only reads the instantaneous value of this register. Initially, this is set to zero to indicate the end of the Control list.
3:0	R	0x0	CCED[3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the CCED, through bit 0 to bit 3 must be zero in this field.

11.2.3.22. 0x0428 HcBulkHeadED

默认值：0x00000000			HcBulkHeadED寄存器（HcBulkHeadED）
位域	类型	默认值	描述
31:4	R/W	0x0	BHED[31:4] BulkHeadED HC traverses the Bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of HC.
3:0	R	0x0	BHED [3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the BHED, through bit 0 to bit 3 must be zero in this field.

11.2.3.23. 0x042C HcBulkCurrentED

默认值：0x00000000			HcBulkCurrentED寄存器（HcBulkCurrentED）
位域	类型	默认值	描述
31:4	R/W	0x0	BCED[31:4] BulkCurrentED This is advanced to the next ED after the HC has served the present one. HC continues processing the list from where it left off in the last Frame. When it reaches the end of the Bulk list, HC checks the ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared. When set, the HCD only reads the instantaneous value of this register. This is initially set to zero to indicate the end of the Bulk list.
3:0	R	0x0	BCED [3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the BCED, through bit 0 to bit 3 must be zero in this field.

11.2.3.24. 0x0430 HcDoneHead

默认值：0x00000000			HcDoneHead寄存器（HcDoneHead）
位域	类型	默认值	描述
31:4	R	0x0	DH[31:4] DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus.
3:0	R	0x0	DH [3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the DH, through bit 0 to bit 3 must be zero in this field.

11.2.3.25. 0x0434 HcFmInterval

默认值：0x00002EDF			HcFmInterval寄存器（HcFmInterval）
位域	类型	默认值	描述
31	R/W	0x0	FIT FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
30:16	R/W	0x0	FSMPS FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun. The field value is calculated by the HCD.
15:14	-	-	-
13:0	R/W	0x2EDF	FI FrameInterval This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999. HCD should store the current value of this field before resetting HC. By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value. HCD may choose to restore the stored value upon the completion of the Reset sequence.

11.2.3.26. 0x0438 HcFmRemaining

默认值：0x00000000			HcFmRemaining寄存器（HcFmRemaining）
位域	类型	默认值	描述
31	R	0x0	FRT FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD for the synchronization between FrameInterval and FrameRemaining.
30:14	-	-	-
13:0	R	0x0	FR FrameRemaining This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, HC re-loads the content with the FrameInterval of HcFmInterval and uses the updated value from the next SOF.

11.2.3.27. 0x043C HcFmNumber

默认值：0x00000000			HcFmNumber寄存器（HcFmNumber）
位域	类型	默认值	描述
31:16	-	-	-
15:0	R	0x0	FN FrameNumber This is incremented when HcFmRemaining is re-loaded. It will be rolled over to 0h after ffffh. When entering the USBOPERATIONAL state, this will be incremented automatically. The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame. After writing to HCCA, HC will set the StartofFrame in HcInterruptStatus.

11.2.3.28. 0x440 HcPeriodicStart

默认值：0x00000000			HcPeriodicStart寄存器（HcPeriodicStart）
位域	类型	默认值	描述
31:14	-	-	-
13:0	R/W	0x0	PS PeriodicStart After a hardware reset, this field is cleared. This is then set by HCD during the HC initialization. The value is calculated roughly as 10% off from HcFmInterval. A typical value will be 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress.

11.2.3.29. 0x444 HcLSThreshold

默认值：0x00000628			HcLSThreshold寄存器（HcLSThreshold）
位域	类型	默认值	描述
31:12	-	-	-
11:0	R/W	0x628	LST LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction. The transaction is started only if FrameRemaining this field. The value is calculated by HCD with the consideration of transmission and setup overhead.

11.2.3.30. 0x448 HcRhDescriptorA

默认值：0x02000001			HcRhDescriptorA寄存器（HcRhDescriptorA）
位域	类型	默认值	描述
31:24	R/W	0x2	POTPGT PowerOnToPowerGoodTime POWER启动时间 This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms.
23:13	-	-	-
12	R/W	0x0	NOCP NoOverCurrentProtection 不支持过流保护 This bit describes how the overcurrent status for the Root Hub ports are reported. When this bit is cleared, the OverCurrentProtectionMode field specifies global or per-port reporting. 0x0：Over-current status is reported collectively for all downstream ports 0x1：No overcurrent protection supported
11	R/W	0x0	OCPM OverCurrentProtectionMode 过流保护模式 This bit describes how the overcurrent status for the Root Hub ports are reported. At reset, this fields should reflect the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection field is cleared. 0x0: over-current status is reported collectively for all downstream ports 0x1: over-current status is reported on a per-port basis
10	R/W	0x0	DT DeviceType This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0.
9	R/W	0x0	NPS NoPowerSwitching 不支持电源开关 These bits are used to specify whether power switching is supported or port are always powered. It is implementationspecific. When this bit is cleared, the PowerSwitchingMode specifies global or per-port switching. 0x0: Ports are power switched，电源可通过开关打开 0x1: Ports are always powered on when the HC is powered on
8	R/W	0x0	PSM PowerSwitchingMode 电源开关模式 This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation-specific. This field is only valid if the NoPowerSwitching field is cleared. 0x0: all ports are powered at the same time. 0x1: each port is powered individually. This mode allows port power to be controlled by either the global switch or perport switching. If the PortPowerControlMask bit is set, the port responds only to port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower).
7:0	R/W	0x1	NDP NumberDownstreamPorts 下行端口的数目 These bits specify the number of downstream ports supported by the Root Hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OpenHCI is 15.

11.2.3.31. 0x44C HcRhDescriptorB

默认值：0x00000000			HcRhDescriptorB寄存器（HcRhDescriptorB）
位域	类型	默认值	描述
31:16	R/W	0x0	PPCM PortPowerControlMask 端口电源控制屏蔽 Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port’s power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode=0), this field is not valid. bit 0: Reserved bit 1: Ganged-power mask on Port #1 bit 2: Ganged-power mask on Port #2 … bit15: Ganged-power mask on Port #15
15:0	R/W	0x0	DR DeviceRemovable Device可移除设置 Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. bit 0: Reserved bit 1: Device attached to Port #1 bit 2: Device attached to Port #2 … bit15: Device attached to Port #15

11.2.3.32. 0x450 HcRhStatus

默认值：0x00000000			HcRhStatus寄存器（HcRhStatus）
位域	类型	默认值	描述
31	W	0x0	CRWE ClearRemoteWakeupEnable 清除远程唤醒使能 Writing a ‘1’ clears DeviceRemoveWakeupEnable. Writing a ‘0’ has no effect.
30:18	-	-	-
17	R/W	0x0	OCIC OverCurrentIndicatorChange 过流状态出现变化 0x0：无变化 0x1：电源的过流状态出现变化，写1清0 This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a ‘1’. Writing a ‘0’ has no effect.
16	R/W	0x0	SetGlobalPower 全局电源使能 在全局电源模式下 0x0：无操作 0x1：所有端口电源闭合 在端口电源模式下，需要配合PortPowerControlMask使用 0x0：无操作 0x1：非屏蔽的端口电源闭合 In global power mode (PowerSwitchingMode=0), This bit is written to ‘1’ to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.
15	R/W	0x0	DRWE (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt. 0x0：ConnectStatusChange is not a remote wakeup event. 0x1：ConnectStatusChange is a remote wakeup event. (write) SetRemoteWakeupEnable Writing a ‘1’ sets DeviceRemoveWakeupEnable. Writing a ‘0’ has no effect.
14:2	-	-	-
1	R/W	0x0	OCI OverCurrentIndicator 过流指示位 0x0：电源工作正常 0x1：电源出现过流的状态 This bit reports overcurrent conditions when the global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented this bit is always ‘0’
0	R/W	0x0	ClearGlobalPower 全局电源断开 在全局电源模式下 0x0：无操作 0x1：所有端口电源断开 在端口电源模式下，需要配合PortPowerControlMask使用 0x0：无操作 0x1：非屏蔽的端口电源断开 In global power mode (PowerSwitchingMode=0), This bit is written to ‘1’ to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.

11.2.3.33. 0x454 HcRhPortStatus

默认值：0x00000080			HcRhPortStatus寄存器（HcRhPortStatus）
位域	类型	默认值	描述
31:21	-	-	-
20	R/W	0x0	PRSC PortResetStatusChange 端口RESET状态改变 This bit is set at the end of the 10-ms port reset signal. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0x0：port reset is not complete 0x1：port reset is complete
19	R/W	0x0	OCIC PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0x0：no change in PortOverCurrentIndicator 0x1：PortOverCurrentIndicator has changed
18	R/W	0x0	PSSC PortSuspendStatusChange This bit is set when the full resume sequence has been completed. This sequence includes the 20-s resume pulse, LS EOP, and 3-ms resychronization delay. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. This bit is also cleared when ResetStatusChange is set. 0x0：resume is not completed 0x1：resume completed
17	R/W	0x0	PESC PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0x0：no change in PortEnableStatus 0x1：change in PortEnableStatus
16	R/W	0x0	CSC ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0x0：no change in CurrentConnectStatus 0x1：change in CurrentConnectStatus Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached.
15:10	-	-	-
9	R/W	0x0	LSDA (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port. When clear, a Full Speed device is attached to this port. This field is valid only when the CurrentConnectStatus is set. 0x0：full speed device attached 0x1：low speed device attached (write) ClearPortPower The HCD clears the PortPowerStatus bit by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.
8	R/W	0x0	PPS (read) PortPowerStatus This bit reflects the port’s power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. HCD sets this bit by writing SetPortPower or SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled is determined by PowerSwitchingMode and PortPort- ControlMask[NDP]. In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower controls this bit. In per-port power switching (PowerSwitchingMode=1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, Current- ConnectStatus,PortEnableStatus, PortSuspendStatus, and Port- ResetStatus should be reset. 0x0：port power is off 0x1：port power is on (write) SetPortPower The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a ‘0’ has no effect. Note: This bit is always reads ‘1b’ if power switching is not supported.
7:5	-	-	-
4	R/W	0x0	PRS (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared. 0x0：port reset signal is not active 0x1：port reset signal is active (write) SetPortReset The HCD sets the port reset signaling by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port.
3	R/W	0x0	POCI (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0x0：no overcurrent condition. 0x1：overcurrent condition detected. (write) ClearSuspendStatus The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has no effect. A resume is initiated only if PortSuspendStatus is set.
2	R/W	0x0	PSS (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspend- StatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBRESUME state. If an upstream resume is in progress, it should propagate to the HC. 0x0：port is not suspended 0x1：port is suspended (write) SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets Connect- StatusChange. This informs the driver that it attempted to suspend a disconnected port.
1	R/W	0x0	PES (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabled- StatusChange to be set. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. This bit is also set, if not already, at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set. 0x0：port is disabled 0x1：port is enabled (write) SetPortEnable The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not set PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port.
0	R/W	0x0	CCS (read) CurrentConnectStatus This bit reflects the current state of the downstream port. 0x0：no device connected 0x1：device connected (write) ClearPortEnable The HCD writes a ‘1’ to this bit to clear the PortEnableStatus bit. Writing a ‘0’ has no effect. The CurrentConnectStatus is not affected by any write. Note: This bit is always read ‘1b’ when the attached device is nonremovable (DeviceRemoveable[NDP]).

11.2.3.34. 0x800 USB_HOST_CTL

默认值：0x00000001			USB HOST控制寄存器（USB Host Control）
位域	类型	默认值	描述
31:26	-	-	-
25	R/W	0x0	Ohci_0_cntsel_i_n OHCI count select 0x0：Normal mode, the counters will count full time 0x1：Simulation mode, the counters will be much shorter than real time
24	R/W	0x0	Ss_simulation_mode_i Simulation Mode 0x0：No effect 0x1：this bit sets the PHY in a non-driving mode so the EHCI can detect device connection. This signal is used only for simulation.
23:20	-	-	-
19	R/W	0x0	App_prt_ovrcur_i Port Overcurrent Indication From Application When asserted by the application, the corresponding port enters Disable state. This signal controls both EHCI and OHCI controller port state machines. Depending on ownership of the port, the corresponding EHCI or OHCI controller generates an Overcurrent Detect interrupt.
18:16	-	-	-
15	R/W	0x0	Ohci_susp_lgcy_i This is a static strap signal. • When tied HIGH and the USB port is owned by OHCI, the signal utmi_suspend_o_n reflects the status of the USB port: (suspended or not suspended). • When tied LOW and the USB port is owned by OHCI, then - utmi_suspend_o_n asserts (0) if all the OHCI ports are suspended, or if the OHCI is in global suspend state (HCFS=USBSUSOPEND). - utmi_suspend_o_n deasserts (1) if any of the OHCI ports are not suspended and OHCI is not in global suspend.
14	R/W	0x0	App_start_clk_i This is an asynchronous primary input to the host core. When the OHCI clocks are suspended, the system has to assert this signal to start the clocks (12 and 48 MHz). This should be deasserted after the clocks are started and before the host is suspended again. (Host is suspended means HCFS = SUSPEND or all the OHCI ports are suspended).
13	R/W	0x0	Ss_autoppd_on_overcur_en_i 0x0：No effect 0x1：This strap signal enables automatic port power disable in the host controller. When this signal is active, if an over-current condition is detected on a powered port and PPC is 1, the PP bit in each affected port is automatically transitioned by the host controller from a 1 to 0, removing power from the port.
12	R/W	0x0	Ss_ulpi_pp2vbus_i 0x0：No effect 0x1：This strap signal enables the function to automatically set/clear the PHY’s port power setting to reflect the Host’s port power setting
11	R/W	0x0	Ss_ena_incr16_i AHB Burst Type INCR16 Enable 0x0：Do not use INCR16; use other enabled INCRX bursts or unspecified length burst INCR 0x1：Use INCR16 when appropriate
10	R/W	0x0	Ss_ena_incr8_i AHB Burst Type INCR8 Enable 0x0：Do not use INCR8; use other enabled INCRX bursts or unspecified length burst INCR 0x1：Use INCR8 when appropriate
9	R/W	0x0	Ss_ena_incr4_i AHB Burst Type INCR4 Enable 0x0：Do not use INCR4; use other enabled INCRX bursts or unspecified length burst INCR 0x1：Use INCR4 when appropriate
8	R/W	0x0	Ss_ena_incrx_align_i Burst Alignment Enable 0x0：Start INCRX burst only on burst x-aligned address 0x1：Normal AHB operation; start bursts on any double word boundary
7:5	-	-	-
4	R/W	0x0	Utmi_word_if 0x0: 8bit 0x1: 16bit
3:1	-	-	-
0	R/W	0x1	ULPI bypass enable 0x0：ULPI enable 0x1：ULPI Disable，use UTMI

11.2.3.35. 0x810 PHY_CTL

默认值：0x00000000			USB PHY控制寄存器（USB PHY Control）
位域	类型	默认值	描述
31:9	-	-	-
8	RW	0x0	BIST_PRE_EN Enable BIST Preparation 0x0：no effect 0x1：txvalid = 0
7	RW	0x0	Loopbackenb Loopback Test Enable 0x0：During data transmission, the receive logic is disabled. 0x1：During data transmission, the receive logic is enabled.
6	RW	0x0	Idpullup Analog ID Input Sample Enable 0x0：ID pin sampling is disabled, and the IDDIG0 output is not valid. 0x1：ID pin sampling is enabled, and the IDDIG0 output is valid.
5	RW	0x0	Vbusvldext External VBUS Valid Indicator（对于HOST无影响） 0x0：Vbus invalid 0x1：Vbus valid
4	-	-	-
3	RW	0x0	Siddq IDDQ Test Enable 0x0：enable internal phy 0x1：disable internal phy
2	RW	0x0	Commononn Common Block Power-Down Control 0x0：In Suspend or Sleep mode, the XO, Bias, and PLL blocks remain powered. 0x1：In Suspend mode, the XO, Bias, and PLL blocks are powered down. In Sleep mode, the Bias and PLL blocks are powered down.
1:0	RW	0x0	Vatestenb Analog Test Pin Select 0x0：Analog test voltages cannot be viewed or applied on either ANALOGTEST or ID0. 0x1：Analog test voltages can be viewed or applied on ID0. 0x2：Analog test voltages can be viewed or applied on ANALOGTEST. 0x3：Reserved. Invalid setting.

11.2.3.36. 0x814 PHY_TEST

默认值：0x00000000			USB PHY测试寄存器（USB PHY Test）
位域	类型	默认值	描述
31:15	-	-	-
14	RW	0x0	Testburnin
13	RW	0x0	Testdataoutsel
12	RW	0x0	Testclk
11:8	RW	0x0	Testaddr
7:0	RW	0x0	Testdatain Test Data Write Bus

11.2.3.37. 0x818 PHY_TUNE

默认值：0x023438E4			USB PHY调节寄存器（USB PHY Tune）
位域	类型	默认值	描述
31:26	-	-	-
25:23	R/W	0x4	Compdistune Disconnect Threshold Adjustment This bus adjusts the voltage level for the threshold used to detect a disconnect event at the host. 0x7：+ 4.5% 0x6：+ 3% 0x5：+ 1.5% 0x4：Design default 0x3：–1.5% 0x2：–3% 0x1：–4.5% 0x0：–6%
22:20	R/W	0x3	Sqrxtune Squelch Threshold Adjustment This bus adjusts the voltage level for the threshold used to detect valid high-speed data. 0x7：–20% 0x6：–15% 0x5：–10% 0x4：–5% 0x3：Design default 0x2：+ 5% 0x1：+ 10% 0x0: + 15%
19	R/W	0x0	Txpreemppulsetune This signal controls the duration for which the HS pre-emphasis current is sourced onto DP0 or DM0. The HS Transmitter pre- emphasis duration is defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and is defined as 1X pre-emphasis duration. This signal is valid only if either TXPREEMPAMPTUNE0[1] or TXPREEMPAMPTUNE0[0] is set to 1’b1. 0 (design default)：2X, long pre-emphasis current duration 1：1X, short pre-emphasis current duration
18:16	R/W	0x4	Otgtune VBUS Valid Threshold Adjustment This bus adjusts the voltage level for the VBUS Valid threshold. 0x7：+ 9% 0x6：+ 6% 0x5：+ 3% 0x4：Design default 0x3：–3% 0x2：–6% 0x1：–9% 0x0：–12%
15:12	R/W	0x3	Txfslstune FS/LS Source Impedance Adjustment This bus adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage, and temperature. 0xf：–5% 0x7：–2.5% 0x3：Design default 0x1：+ 2.5% 0x0：+ 5%
11:8	R/W	0x8	Txvreftune This bus adjusts the high-speed DC level voltage. 0xf：+ 24% 0xe：+ 22% 0xd：+ 20% 0xc：+ 18% 0xb：+ 16% 0xa：+ 14% 0x9：+ 12% 0x8：+ 10% 0x7：+ 8% 0x6：+ 6% 0x5：+ 4% 0x4：+ 2% 0x3：Design default 0x2：–2% 0x1：–4% 0x0：–6%
7:6	R/W	0x3	Txhsxvtune Transmitter High-Speed Crossover Adjustment This bus adjusts the voltage at which the DP0 and DM0 signals cross while transmitting in HS mode. 0x0：Reserved 0x1：–15 mV 0x2：+ 15 mV 0x3：Default setting
5:4	R/W	0x2	Txrisetune HS Transmitter Rise/Fall Time Adjustment This bus adjusts the rise/fall times of the high-speed waveform. 0x0：+ 10% 0x1：Design default 0x2：–20% 0x3：–40%
3:2	R/W	0x1	Txrestune USB Source Impedance Adjustment In some applications, there can be significant series resistance on the D+ and D– paths between the transceiver and cable. This bus adjusts the driver source impedance to compensate for added series resistance on the USB. Note: Any setting other than the default can result in source impedance variation across process, voltage, and temperature conditions that does not meet USB 2.0 specification limits. 0x0：Source impedance is increased by approximately 1.5 Ω. 0x1：Design default 0x2：Source impedance is decreased by approximately 2 Ω. 0x3：Source impedance is decreased by approximately 4 Ω.
1:0	R/W	0x0	Txpreempamptune HS Transmitter Pre-Emphasis Current Control This signal controls the amount of current sourced to DP0 and DM0 after a J-to-K or K-to-J transition. The HS Transmitter pre- emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 μA and is defined as 1X pre-emphasis current. 0x0 (design default): HS Transmitter pre-emphasis is disabled. 0x1: HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current. 0x2: HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current. 0x3: HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current.

11.2.3.38. 0x824 PHY_STS

默认值：0x00000008			USB PHY状态寄存器（USB PHY Status）
位域	类型	默认值	描述
31:4	-	-	-
3:0	RO	0x8	Testdataout Test Data Read Bus